Magnetic memories, particularly magnetic random access memories (MRAMs), have drawn increasing interest due to their potential for high read/write speed, excellent endurance, non-volatility and low power consumption during operation. An MRAM can store information utilizing magnetic materials as an information recording medium. One type of MRAM is a spin transfer torque random access memory (STT-RAM). STT-RAM utilizes magnetic junctions written at least in part by a current driven through the magnetic junction. A spin polarized current driven through the magnetic junction exerts a spin torque on the magnetic moments in the magnetic junction. As a result, layer(s) having magnetic moments that are responsive to the spin torque may be switched to a desired state.
For example, FIG. 1 depicts a conventional STT-RAM 5 including conventional magnetic tunneling junctions (MTJ) 10. The conventional MTJs 10 are separated by a pitch and have widths, w. Typically, the pitch is at least two hundred to three hundred microns or more. The width of the MTJs 10 is typically approximately ninety to one hundred and twenty microns or more. However, an isolated MTJ 10, which is for example, at least three hundred nanometers or more from the nearest MTJ, may be fabricated on the order of twenty-two nanometers or more. The conventional MTJ 10 typically resides on a bottom contact (not shown), uses conventional seed layer(s) 12 and includes a conventional antiferromagnetic (AFM) layer 14, a conventional pinned layer 16, a conventional tunneling barrier layer 18, a conventional free layer 20, and a conventional capping layer 22. A top contact (not shown) typically resides on the MTJ 10. A dielectric capping layer 24 typically covers the MTJs 10.
To switch the magnetization 21 of the conventional free layer 20, a current is driven in the CPP direction. When a sufficient current is driven between the top contact and the bottom contact, the magnetization 21 of the conventional free layer 20 may switch to be parallel or antiparallel to the magnetization 17 of the conventional pinned layer 16. The differences in magnetic configurations correspond to different magnetoresistances and thus different logical states (e.g. a logical “0” and a logical “1”) of the conventional MTJ 10. Thus, by reading the tunneling magnetoresistance (TMR) of the conventional MTJ 10 the state of the conventional MTJ can be determined.
FIG. 2 depicts a conventional method 50 for fabricating the conventional MTJs 10 in the conventional STT-RAM 5. The stack for the MTJs 10 is deposited and masked, via step 52. For example, the layers 12, 14, 16, 18, 20 and 22 may be deposited across the surface of a wafer. A hard mask layer is also deposited. The hard mask may include materials such as Ta or W.
A pattern for the STT-RAM 5 is transferred to the hard mask using a reactive ion etch (RIE), via step 54. Typically, a photoresist pattern corresponding to the MTJs 10 is provided on the hard mask. The photoresist mask covers the regions in which the MTJs are desired to be formed. In an RIE chamber, a reactive gas appropriate for the hard mask is introduced at a low pressure, typically on the order of a few milliTorr. For example, F or CL may be used for a Ta or W hard mask. The RIE is then performed in step 54 to chemically remove portions of the hard mask layer exposed by the photoresist mask. Consequently, the pattern developed in the photoresist mask may be accurately transferred to the hard mask in step 54.
Once the RIE is performed, the wafer containing the memory 5 is removed from the RIE chamber and transferred to an ion milling chamber, via step 56. During step 56, the wafer is typically exposed to ambient. In other words, the memory 5 is exposed to air. The MTJs are then defined via angled ion milling, via step 58. To perform step 58, the ion milling chamber is evacuated, typically to well below 10−5 Torr. The low pressure is desired to allow ions, for example from an ion gun, to reach the surface of the wafer and remove portions of the MTJ stack exposed by the hard mask. In contrast to the RIE performed in step 54, step 58 is considered to be a physical, rather than chemical, process. Thus, the ions used in step 58 are desired to be chemically non-reactive with the layers 12, 14, 16, 18 and 20 of the stack. The conventional capping layer 24 may then be deposited, via step 60. Fabrication of the conventional STT-RAM 5 may then be completed.
Although the conventional STT-RAM 5 may be fabricated, there are drawbacks. Ion milling at an angle in step 58 may limit the extent to which the pitch of the conventional STT-RAM 5 may be reduced. Further, it has been determined that the yield of the method 50 may be low. For example, there may be large variations in electrical properties of the conventional MTJs 10. For example, the tunneling magnetoresistance (TMR) and resistance area produce (RA) of the conventional MTJs 10 may differ. These differences may be sufficiently large that the conventional STT-RAM 5 is unusable. Thus, the yield for the conventional method 50 may be low.
Accordingly, what is needed is a method and system that may improve performance of, reduce variations in performance of and, therefore, enhance the yield for the spin transfer torque based memories. The method and system described herein address such a need.